Fault-Independent Test-Generation for Software-Based Self-Testing

Software-based self-test (SBST) is being widely used in both manufacturing and in-the-field testing of processor-based devices and Systems-on-Chips. Unfortunately, the stuck-at fault model is increasingly inadequate to match the new and different types of defects in the most recent semiconductor technologies, while the explicit and separate targeting of every fault model in SBST is cumbersome due to the high complexity of the test-generation process, the lack of automation tools, and the high CPU-intensity of the fault-simulation process. Moreover, defects in advanced semiconductor technologies are not always covered by the most commonly used fault-models, and the probability of defect-escapes increases even more. To overcome these shortcomings we propose the first fault-independent SBST method. The proposed method is almost fully automated, it offers high coverage of non-modeled faults by means of a novel SBST-oriented probabilistic metric, and it is very fast as it omits the time-consuming test-generation/fault-simulation processes. Extensive experiments on the OpenRISC OR1200 processor show the advantages of the proposed method

Fault-Independent Test-Generation for Software-Based Self-Testing

Software-based self-test (SBST) is being widely used in both manufacturing and in-the-field testing of processor-based devices and Systems-on-Chips. Unfortunately, the stuck-at fault model is increasingly inadequate to match the new and different types of defects in the most recent semiconductor technologies, while the explicit and separate targeting of every fault model in SBST is cumbersome due to the high complexity of the test-generation process, the lack of automation tools, and the high CPU-intensity of the fault-simulation process. Moreover, defects in advanced semiconductor technologies are not always covered by the most commonly used fault-models, and the probability of defect-escapes increases even more. To overcome these shortcomings we propose the first fault-independent SBST method. The proposed method is almost fully automated, it offers high coverage of non-modeled faults by means of a novel SBST-oriented probabilistic metric, and it is very fast as it omits the time-consuming test-generation/fault-simulation processes. Extensive experiments on the OpenRISC OR1200 processor show the advantages of the proposed method

A machine learning-based approach to optimize repair and increase yield of embedded flash memories in automotive systems-on-chip

Nowadays, Embedded Flash Memory cores occupy a significant portion of Automotive Systems-on-Chip area, therefore strongly contributing to the final yield of the devices. Redundancy strategies play a key role in this context; in case of memory failures, a set of spare word- and bit-lines are allocated by a replacement algorithm that complements the memory testing procedure. In this work, we show that replacement algorithms, which are heavily constrained in terms of execution time, may be slightly inaccurate and lead to classify a repairable memory core as unrepairable. We denote this situation as Flash memory false fail. The proposed approach aims at identifying false fails by using a Machine Learning approach that exploits a feature extraction strategy based on shape recognition. Experimental results carried out on the manufacturing data show a high capability of predicting false fails

Recent Trends and Perspectives on Defect-Oriented Testing

Electronics employed in modern safety-critical systems require severe qualification during the manufacturing process and in the field, to prevent fault effects from manifesting themselves as critical failures during mission operations. Traditional fault models are not sufficient anymore to guarantee the required quality levels for chips utilized in mission-critical applications. The research community and industry have been investigating new test approaches such as device-aware test, cell-aware test, path-delay test, and even test methodologies based on the analysis of manufacturing data to move the scope from OPPM to OPPB. This special session presents four contributions, from academic researchers and industry professionals, to enable better chip quality. We present results on various activities towards this objective, including device-aware test, software-based self-test, and memory test

Test, Reliability and Functional Safety Trends for Automotive System-on-Chip

This paper encompasses three contributions by industry professionals and university researchers. The contributions describe different trends in automotive products, including both manufacturing test and run-time reliability strategies. The subjects considered in this session deal with critical factors, from optimizing the final test before shipment to market to in-field reliability during operative life

Integrative epigenome-wide analysis demonstrates that DNA methylation may mediate genetic risk in inflammatory bowel disease

Epigenetic alterations may provide important insights into gene-environment interaction in inflammatory bowel disease (IBD). Here we observe epigenome-wide DNA methylation differences in 240 newly-diagnosed IBD cases and 190 controls. These include 439 differentially methylated positions (DMPs) and 5 differentially methylated regions (DMRs), which we study in detail using whole genome bisulphite sequencing. We replicate the top DMP (RPS6KA2) and DMRs (VMP1, ITGB2 and TXK) in an independent cohort. Using paired genetic and epigenetic data, we delineate methylation quantitative trait loci; VMP1/microRNA-21 methylation associates with two polymorphisms in linkage disequilibrium with a known IBD susceptibility variant. Separated cell data shows that IBD-associated hypermethylation within the TXK promoter region negatively correlates with gene expression in whole-blood and CD8+ T cells, but not other cell types. Thus, site-specific DNA methylation changes in IBD relate to underlying genotype and associate with cell-specific alteration in gene expression

[Isolated hydatid cyst of the kidney].

BACKGROUND: A hydatid cyst is a parasitic disease caused by the tapeworm Echinococcus granulosus. Kidney involvement represents 4% of all cases, and is rare compared to that in the liver or lung, even more as an isolated site of infection. We present a case report of a woman with septic status, cutaneous fistula and a renal cystic mass revealed to be a solitary hydatid cyst of the kidney. METHODS: A 60-year-old woman was referred acutely by another hospital to our department because of septic fever, cutaneous lumbar fistula and a left kidney cystic mass of 10 x 8 cm. We suspected a renal abscess and the patient underwent immediate left nephrectomy. RESULTS: We performed an extraperitoneal nephrectomy with a lumbar access under the 12th rib with complete resection of the fistula. The histopathological examination revealed it to be a hydatid cyst involving 2/3 of the kidney. After surgery a medical therapy with albendazol was administrated for 6 months, and the patient did not have any other localization 24 months after surgery. CONCLUSIONS: An isolated renal hydatid cyst presenting as cutaneous fistula with a septic status is a very rare condition. A pre-surgical diagnosis is not always possible as in this case. The surgical therapy (nephron-sparing or radical) is the key of the success and a medical therapy after surgery is recommended to prevent other localizations of this parasitic disease

Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks

The IEEE 1687 standard describes reconfigurable structures allowing to flexibly access the instruments existing within devices (e.g., to support test, debug, calibration, etc.), by the use of configurable modules acting as controllable switches. The increasing adoption of this standard requires the availability of algorithms and tools to automate its usage. Since the resulting networks could inevitably be affected by defects which may prevent their correct usage, solutions allowing not only to test against these defects, but also to diagnose them (i.e., to identify the location of possible faults) are of uttermost importance. This paper proposes a method to automatically generate suitable test stimuli: by applying them and observing the output of the network one can not only detect possible faults, but also identify the fault responsible for the misbehavior. Experimental results gathered on a set of benchmark networks with a prototypical tool implementing the proposed techniques show the feasibility and provide a first idea about the length of the required input stimuli